Table 14.45. Registers for OUT1,2,3,4,5,6,7,8,9 as per Above for OUT0
Register Address Description (Same as) Address
0x010D OUT1_PDN, OUT1_OE, OUT1_RDIV_FORCE2 0x0108
0x010E OUT1_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x010F OUT1_CM, OUT1_AMPL 0x010A
0x0110 OUT1_MUX_SEL, OUT1_VDD_SEL_EN, OUT1_VDD_SEL, OUT1_INV 0x010B
0x0112 OUT2_PDN, OUT2_OE, OUT2_RDIV_FORCE2 0x0108
0x0113 OUT2_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x0114 OUT2_CM, OUT2_AMPL 0x010A
0x0115 OUT2_MUX_SEL, OUT2_VDD_SEL_EN, OUT2_VDD_SEL, OUT2_INV 0x010B
0x0117 OUT3_PDN, OUT3_OE, OUT3_RDIV_FORCE2 0x0108
0x0118 OUT3_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x0119 OUT3_CM, OUT3_AMPL 0x010A
0x011A OUT3_MUX_SEL, OUT3_VDD_SEL_EN, OUT3_VDD_SEL, OUT3_INV 0x010B
0x011C OUT4_PDN, OUT4_OE, OUT4_RDIV_FORCE2 0x0108
0x011D OUT4_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x011E OUT4_CM, OUT4_AMPL 0x010A
0x011F OUT4_MUX_SEL, OUT4_VDD_SEL_EN, OUT4_VDD_SEL, OUT4_INV 0x010B
0x0121 OUT5_PDN, OUT5_OE, OUT5_RDIV_FORCE2 0x0108
0x0122 OUT5_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x0123 OUT5_CM, OUT5_AMPL 0x010A
0x0124 OUT5_MUX_SEL, OUT5_VDD_SEL_EN, OUT5_VDD_SEL, OUT5_INV 0x010B
0x0126 OUT6_PDN, OUT6_OE, OUT6_RDIV_FORCE2 0x0108
0x0127 OUT6_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x0128 OUT6_CM, OUT6_AMPL 0x010A
0x0129 OUT6_MUX_SEL, OUT6_VDD_SEL_EN, OUT6_VDD_SEL, OUT6_INV 0x010B
0x012B OUT7_PDN, OUT7_OE, OUT7_RDIV_FORCE2 0x0108
0x012C OUT7_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x012D OUT7_CM, OUT7_AMPL 0x010A
0x012E OUT7_MUX_SEL, OUT7_VDD_SEL_EN, OUT7_VDD_SEL, OUT7_INV 0x010B
0x0130 OUT8_PDN, OUT8_OE, OUT8_RDIV_FORCE2 0x0108
0x0131 OUT8_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x0132 OUT8_CM, OUT8_AMPL 0x010A
0x0133 OUT8_MUX_SEL, OUT8_VDD_SEL_EN, OUT8_VDD_SEL, OUT8_INV 0x010B
0x013A OUT9_PDN, OUT9_OE, OUT9_RDIV_FORCE2 0x0108
0x013B OUT9_FORMAT, _SYNC_EN, DIS_STATE, _CMOS_DRV 0x0109
0x013C OUT9_CM, OUT9_AMPL 0x010A
Si5341, Si5340 Rev D Family Reference Manual • Register Map
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